Patent Number: 7,712,013

Title: Block decoding methods and apparatus

Abstract: In an embodiment, a method includes performing a redundancy check to determine if a baseline bit sequence is compliant. When the baseline bit sequence is not compliant, the method additionally includes performing an iterative process until a compliant, candidate bit sequence is identified. The iterative process includes identifying one or more existing branches within a conceptual tree diagram, calculating scores for potential paths branching from the one or more existing branches, and performing a subsequent redundancy check on a next candidate bit sequence, which corresponds to a potential path that has a next lowest score, to determine if the next candidate bit sequence is compliant.

Inventors: Griniasty; Meir (Kfar-Azar, IL), Altahan; Moti (Rishon-Le-Zion, IL)

Assignee: Intel Corporation

International Classification: H03M 13/03 (20060101)

Expiration Date: 5/04/12018