Patent Number: 7,712,067

Title: Method and apparatus for facilitating effective and efficient optimization of short-path timing constraints

Abstract: A method for connecting a first and second component in a logic device is disclosed. A path is generated between the first and second components with an appropriate amount of delay to satisfy short-path timing constraints that define a minimum delay on the path. A first interconnect line from a plurality of interconnect lines and a second interconnect line to connect with the first interconnect line sub-optimally from a delay minimization perspective are selected in order to satisfy the short-path timing constraints.

Inventors: Fung; Ryan (Mississauga, CA), Chan; Michael (Scarborough, CA)

Assignee: Altera Corporation

International Classification: G06F 17/50 (20060101)

Expiration Date: 5/04/12018