Patent Number: 7,713,804

Title: Method of forming an oxide isolated metal silicon-gate JFET

Abstract: A JFET structure with self-aligned metal source, drain and gate contacts with very low resistivity and very small feature sizes. Small source, drain and gate openings are etched in a thin dielectric layer which has a thickness set according to the desired source, gate and drain opening sizes, said dielectric layer having a nitride top layer. Metal is deposited on top of said dielectric layer to fill said openings and the metal is polished back to the top of the dielectric layer to achieve thin source, drain and gate contacts. Some embodiments include an anti-leakage poly-silicon layer lining the contact holes and all embodiments where spiking may occur include a barrier metal layer.

Inventors: Vora; Madhukar B. (Los Gatos, CA), Kapoor; Ashok K. (Palo Alto, CA)

Assignee: SuVolta, Inc.

International Classification: H01L 21/337 (20060101)

Expiration Date: 5/11/12018