Patent Number: 7,714,565

Title: Methods and apparatus for testing delay locked loops and clock skew

Abstract: According to the methods of the invention, a further delayed DLL signal is compared to the reference clock and a delayed reference clock signal is compared to a DLL signal. These two comparisons are performed on the signal and on the signal. The delay introduced by the methods of the invention is preferably adjustable based on the results of a process monitor test. The process monitor test can be run continuously and accounts for process, voltage and temperature. The methods of the invention can also be used to test for clock skew in a clock tree on a chip.

Inventors: Abuhamdeh; Zahi S. (Billerica, MA), D'Alessandro; Vincent (Burlington, MA)

Assignee: Transwitch Corporation

International Classification: G01R 23/175 (20060101); G01R 23/12 (20060101); H03L 7/06 (20060101)

Expiration Date: 5/11/12018