Patent Number: 7,715,143

Title: Delta-sigma PLL using fractional divider from a multiphase ring oscillator

Abstract: A disk drive controller includes a servo system operable to associate a time stamp with an arrival of a servo wedge, a firmware loop and core PLLs in the read channel. The firmware loop is operable to determine a period between the arrival of a pair of consecutive servo wedges and produce a desired frequency of when to read/write data to disk based on the period between the arrival of a pair of consecutive servo wedges. Processing circuitry is operable to adjust a clock signal, wherein the clock signal itself is not locked to the data and produce a fine control signal for the core PLLs in the read channel. These core PLLs are operable to determine a phase and/or frequency associated with when an analog signal is sampled and/or written to disk, wherein these core PLLs comprises Fractional N Sigma Delta PLLs.

Inventors: Bliss; William Gene (Thornton, CO), Chambers; Mark (Laguna Hills, CA)

Assignee: Broadcom Corporation

International Classification: G11B 21/04 (20060101)

Expiration Date: 5/11/12018