Patent Number: 7,715,242

Title: Erasing method of non-volatile memory

Abstract: An erasing method of a non-volatile memory is provided. The non-volatile memory includes a control gate disposed in a substrate, a floating gate, a gate oxide layer disposed between the floating gate and the substrate, a source region disposed in the substrate, a drain region disposed in the substrate, a first dielectric layer disposed on the floating gate, a second dielectric layer disposed on sidewalls of the floating gate, and an erase gate. The erasing method includes applying a first voltage on the control gate, applying a second voltage on the drain, applying a third voltage on the source, applying a fourth voltage on the erase gate, and applying a fifth voltage on the substrate, such that electrons are drawn from the floating gate to the erase gate to be erased.

Inventors: Hung; Chih-Lung (Hsinchu, TW)

Assignee: Episil Technologies Inc.

International Classification: G11C 16/00 (20060101)

Expiration Date: 5/11/12018