Patent Number: 7,715,263

Title: Semiconductor memory device

Abstract: A semiconductor memory device includes a memory cell array and a voltage generation circuit for generating a voltage applied to the memory cell array, in which a plurality of drive MOS transistors having different width dimensions are selectively connected in parallel between an output line and the ground. The voltage is adjusted in response to the surrounding temperature in such a way that a prescribed number of drive MOS transistors selected from among the plurality of MOS transistors are normally and simultaneously driven. Thus, it is possible to precisely adjust the voltage in units of adjustment corresponding to differences of width dimensions without degrading the performance of the semiconductor memory device in a low current consumption mode.

Inventors: Yamamoto; Koki (Tokyo, JP)

Assignee: Elpida Memory, Inc.

International Classification: G11C 7/04 (20060101)

Expiration Date: 5/11/12018