Patent Number: 7,715,271

Title: Using dedicated read output path to reduce unregistered read access time for a FPGA embedded memory

Abstract: A memory unit includes width decoding logic enabling data to be accessed in a memory array at different data widths. To improve memory access speed, the memory unit also includes dedicated read output paths for accessing data at the full data width of the memory array. The dedicated read output paths bypass the width decoding logic and provide data from the memory array directly to a data bus, thereby providing improved memory performance when width decoding is not needed. The memory unit can be incorporated in programmable devices and a programmable device configuration can select either the read bypass paths or the width decoding logic. Hardware applications that require width decoding and improved memory access speed can utilize additional programmable device resources outside the memory unit to register the full width data from the memory unit and convert it to a different data width.

Inventors: Yu; Haiming (San Jose, CA), Koay; Wei Yee (Penang, MY)

Assignee: Altera Corporation

International Classification: G11C 8/02 (20060101)

Expiration Date: 5/11/12018