Patent Number: 7,716,549

Title: Semiconductor apparatus and testing method

Abstract: A semiconductor apparatus comprising: a plurality of memory circuits each including a memory and an input/output selector, the memory having a plurality of memory cells and a plurality of input/output circuits respectively corresponding to the memory cells; and an incorporated self-test circuit that executes a quality test for the memory, wherein the input/output selector selects one of the input/output circuits and successively outputs data signals to the incorporated self-test circuit, the data signals read by the one of the input/output circuits from the corresponding memory cells.

Inventors: Iizuka; Yoshikazu (Kawasaki, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: G01R 31/28 (20060101)

Expiration Date: 5/11/12018