Patent Number: 7,732,911

Title: Semiconductor packaging substrate improving capability of electrostatic dissipation

Abstract: A semiconductor packaging substrate with improved capability of electrostatic dissipation comprises a dielectric layer, a plurality of leads, a plurality of first electrostatic guiding traces, a plurality of second electrostatic guiding traces and a solder mask. The first electrostatic guiding traces and the second electrostatic guiding traces are formed in pairs in a plurality of electrostatic dissipation regions on the dielectric layer, where each pair of the first and second electrostatic guiding traces are disposed in equal line spacing and are electrically isolated from each other. The solder mask partially covers the leads but exposes the first electrostatic guiding traces and the second electrostatic guiding traces. The first electrostatic guiding traces are connected to some of the leads to enhance protection against electrostatic discharge.

Inventors: Chen; Tsung-Lung (Tainan, TW), Li; Ming-Hsun (Tainan, TW)

Assignee: ChipMOS Technologies Inc.

International Classification: H01L 23/48 (20060101); H01L 23/52 (20060101)

Expiration Date: 2022-06-08 0:00:00