Patent Number: 7,733,124

Title: Method and apparatus for PLD having shared storage elements

Abstract: A programmable logic device (PLD) includes a core region having a plurality of logical array blocks (LABs). Each one of the plurality of logical array blocks include a plurality of logic elements capable of communicating with each other through interconnections defined within each logical array block. The logic elements include a look up table (LUT), wherein a LUT of a first logic element and a LUT of a second logic element share a register. In one embodiment, more than two logic elements may share a register. Thus, the embodiments provide for the ability to vary sequential logic, e.g., registers, instead of rigidly fixing the sequential logic and consequently the ratio of combinatorial logic to sequential logic.

Inventors: Duwel; Keith (San Jose, CA), Hutton; Michael D. (Mountain View, CA)

Assignee: Altera Corporation

International Classification: H03K 19/177 (20060101)

Expiration Date: 2022-06-08 0:00:00