Patent Number: 7,737,553

Title: Semiconductor device

Abstract: Fine-pitch first and second bonding pads are formed on a chip along its perimeter. The first bonding pads are formed at the peripheral parts on the chip, while the second bonding pads are formed inside the peripheral parts. An ESD protection circuit is connected to the first bonding pad, and an I/O circuit is connected to the second bonding pad. First and second bonding wires connect the first and second bonding pads to the same package pin, respectively. The second bonding wire is configured to be sufficiently longer than the first bonding wire, regardless of the pitch of the first bonding pads.

Inventors: Shibata; Osamu (Nishinomiya, JP), Saito; Yoshiyuki (Katano, JP)

Assignee: Panasonic Corporation

International Classification: H01L 23/52 (20060101)

Expiration Date: 2022-06-15 0:00:00