Patent Number: 7,765,351

Title: High bandwidth low-latency semaphore mapped protocol (SMP) for multi-core systems on chips

Abstract: A system and method for dynamically managing movement of semaphore data within the system. The system includes, but is no limited to, a plurality of functional units communicating over the network, a memory device communication with the plurality of functional units over the network, and at least one semaphore storage unit communicating with the plurality of functional unites and the memory device over the network. The plurality of functional units include a plurality of functional unit memory locations. The memory device includes a plurality of memory device memory locations. The at least one semaphore storage unit includes a plurality of semaphore storage unit memory locations. The at least one semaphore storage unit controls dynamic movement of the semaphore data among the plurality of functional unit memory locations, the plurality of memory device memory locations, the plurality of semaphore storage unit memory locations, and any combinations therof.

Inventors: Nsame; Pascal A. (Colchester, VT), Polson; Anthony D. (Jericho, VT), Pratt; Nancy H. (Essex Junction, VT), Ventrone; Sebastian T. (Burlington, VT)

Assignee: International Business Machines Corporation

International Classification: G06F 12/00 (20060101)

Expiration Date: 7/27/12018