Patent Number: 7,765,352

Title: Reducing core wake-up latency in a computer system

Abstract: A power control unit (PCU) may reduce the core wake-up latency in a computer system by concurrently waking-up the remaining cores after the first core is woken-up. The power control unit may detect arrival of a first, second, and a third interrupt directed at a first, second, and a third core. The power control unit may check whether the second interrupt occurs within a first period, wherein the first period is counted after waking-up of the first core is complete. The power control unit may then wake-up the second and the third core concurrently if the second interrupt occurs within the first period after the wake-up activity of the first core is complete. The first period may at least equal twice the time required for a first credit to be returned and next credit to be accepted.

Inventors: Pudipeddi; Bharadwaj (San Jose, CA), Burns; James S. (Cupertino, CA)

Assignee: Intel Corporation

International Classification: G06F 13/24 (20060101)

Expiration Date: 7/27/12018