Patent Number: 7,765,366

Title: Memory micro-tiling

Abstract: According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic and a transaction assembler. The assignment logic receives a request to access a memory channel. The transaction assembler combines the request into one or more additional requests to access two or more independently addressable subchannels within the channel.

Inventors: Akiyama; James (Beaverton, OR), Osborne; Randy B. (Beaverton, OR), Clifford; William H. (Gig Harbor, WA)

Assignee: Intel Corporation

International Classification: G06F 12/00 (20060101); G06F 13/00 (20060101); G06F 13/28 (20060101)

Expiration Date: 7/27/12018