Patent Number: 7,765,384

Title: Universal register rename mechanism for targets of different instruction types in a microprocessor

Abstract: A unified register rename mechanism for targets of different instruction types is provided in a microprocessor. The universal rename mechanism renames destinations of different instruction types using a single rename structure. Thus, an instruction that is updating a floating point register (FPR) can be renamed along with an instruction that is updating a general purpose register (GPR) or vector multimedia extensions (VMX) instructions register (VR) using the same rename structure because the number of architected states for GPR is the same as the number of architected states for FPR and VR. Each destination tag (DTAG) is assigned to one destination. A floating point instruction may be assigned to a DTAG, and then a fixed point instruction may be assigned to the next DTAG and so forth. With a universal rename mechanism, significant silicon and power can be saved by having only one rename structure for all instruction types.

Inventors: Le; Hung Q. (Austin, TX), Nguyen; Dung Q. (Austin, TX), Sinharoy; Balaram (Poughkeepsie, NY)

Assignee: International Business Machines Corporation

International Classification: G06F 9/30 (20060101)

Expiration Date: 7/27/12018