Patent Number: 7,765,446

Title: Method for testing semiconductor integrated circuit and method for verifying design rules

Abstract: A method is provided for testing a semiconductor integrated circuit by utilizing a scan path circuit provided to detect the degeneracy fault in the semiconductor integrated circuit, and bringing scan chains to states in which shift resistor operations can be effected for the input of patterns by which a glitch fault and the IR-DROP fault between the scan chains can be detected.

Inventors: Nobekawa; Tomoko (Osaka, JP)

Assignee: Panasonic Corporation

International Classification: G01R 31/28 (20060101)

Expiration Date: 7/27/12018