Patent Number: 7,769,981

Title: Row of floating point accumulators coupled to respective PEs in uppermost row of PE array for performing addition operation

Abstract: Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support floating-point operations, the parallel processor uses floating-point accumulators and a flag for floating-point multiplication. Using the parallel processor, it is possible to process a geometric transformation operation in a 3-dimensional (3D) graphics process at low cost. Also, the cost of a bus width for instructions can be minimized by a partitioned Single-Instruction Multiple-Data (SIMD) method and a method of conditionally executing instructions.

Inventors: Lyuh; Chun Gi (Daejeon, KR), Yang; Yil Suk (Daejeon, KR), Heo; Se Wan (Busan, KR), Yeo; Soon Il (Daejeon, KR), Roh; Tae Moon (Daejeon, KR), Kim; Jong Dae (Daejeon, KR), Kim; Ki Chul (Seoul, KR), Yoo; Se Hoon (Seoul, KR)

Assignee: Electronics and Telecommunications Research Institute

International Classification: G06F 15/80 (20060101)

Expiration Date: 8/03/12018