Patent Number: 7,769,987

Title: Single hot forward interconnect scheme for delayed execution pipelines

Abstract: A method and apparatus for forwarding data in a processor. The method includes providing at least one cascaded delayed execution pipeline unit having a first pipeline and a second pipeline, wherein the second pipeline executes instructions in a common issue group in a delayed manner relative to the first pipeline. The method further includes determining if a first instruction being executed in the first pipeline modifies data in a data register which is accessed by a second instruction being executed in the second pipeline. If the first instruction being executed in the first pipeline modifies data in the data register which is accessed by the second instruction being executed in the second pipeline, the modified data is forwarded from the first pipeline to the second pipeline.

Inventors: Luick; David Arnold (Rochester, MN)

Assignee: International Business Machines Corporation

International Classification: G06F 9/38 (20060101)

Expiration Date: 8/03/12018