Patent Number: 7,785,927

Title: Multi-die wafer level packaging

Abstract: A semiconductor die package is provided. The semiconductor die package includes a plurality of dies arranged in a stacked configuration. Through-silicon vias are formed in the lower or intermediate dies to allow electrical connections to dies stacked above. The lower die is positioned face up and has redistribution lines electrically coupling underlying semiconductor components to the through-silicon vias. The dies stacked above the lower die may be oriented face up such that the contact pads are facing away from the lower die or flipped such that the contact pads are facing the lower die. The stacked dies may be electrically coupled to the redistribution lines via wire bonding or solder balls. Additionally, the lower die may have another set of redistribution lines on an opposing side from the stacked dies to reroute the vias to a different pin-out configuration.

Inventors: Chen; Chen-Shien (Zhubei, TW), Ching; Kai-Ming (Jhudong Township, TW), Chen; Chih-Hua (Taipei, TW), Kuo; Chen-Cheng (Chu-Pei, TW)

Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.

International Classification: H01L 21/98 (20060101)

Expiration Date: 8/31/12018