Patent Number: 7,785,950

Title: Dual stress memory technique method and related structure

Abstract: A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200.degree. C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.

Inventors: Fang; Sunfei (LaGrangeville, NY), Kim; Jun Jung (Fishkill, NY), Luo; Zhijiong (Carmel, NY), Ng; Hung Y. (New Milford, NJ), Rovedo; Nivo (LaGrangeville, NY), Teh; Young Way (Singapore, SG)

Assignee: International Business Machines Corporation

International Classification: H01L 21/8238 (20060101); H01L 21/469 (20060101)

Expiration Date: 8/31/12018