Patent Number: 7,785,951

Title: Methods of forming integrated circuit devices having tensile and compressive stress layers therein and devices formed thereby

Abstract: Methods of forming integrated circuit devices include forming first, second and third gate electrodes on a semiconductor substrate. A first stress film is provided that covers the first gate electrode and at least a first portion of the third gate electrode. The first stress film has a sufficiently high internal stress characteristic to impart a net compressive stress in a first portion of the semiconductor substrate extending opposite the first gate electrode. A second stress film is also provided. The second stress film covers the second gate electrode and at least a second portion of the third gate electrode. The second stress film has a sufficiently high internal stress characteristic to impart a net tensile stress in a second portion of the semiconductor substrate extending opposite the second gate electrode. The second stress film has an upper surface that is coplanar with an upper surface of the first stress film at a location adjacent the third gate electrode.

Inventors: Nam; Seo-woo (Gyeonggi-do, KR), Yoon; Il-young (Gyeonggi-do, KR), Choo; Jae-ouk (Gyeonggi-do, KR), Shin; Hong-jae (Seoul, KR), Lee; Nae-in (Seoul, KR)

Assignee: Samsung Electronics Co., Ltd.

International Classification: H01L 21/8238 (20060101)

Expiration Date: 8/31/12018