Patent Number: 7,785,961

Title: Trench DRAM cell with vertical device and buried word lines

Abstract: A DRAM array having trench capacitor cells of potentially 4F.sup.2 surface area (F being the photolithographic minimum feature width), and a process for fabricating such an array. The array has a cross-point cell layout in which a memory cell is located at the intersection of each bit line and each word line. Each cell in the array has a vertical device such as a transistor, with the source, drain, and channel regions of the transistor being formed from epitaxially grown single crystal silicon. The vertical transistor is formed above the trench capacitor.

Inventors: Noble; Wendell P. (Milton, VT)

Assignee: Micron Technology, Inc.

International Classification: H01L 21/8242 (20060101)

Expiration Date: 8/31/12018