Patent Number: 7,785,966

Title: Method for fabricating floating gates structures with reduced and more uniform forward tunneling voltages

Abstract: An improved method for fabricating floating gate structures of flash memory cells having reduced and more uniform forward tunneling voltages. The method may include the steps of: forming at least two floating gates over a substrate; forming a mask over each of the floating gates, each of the masks having a portion, adjacent to a tip of a respective one of the floating gates, of a given thickness, wherein the given thicknesses of the mask portions are different from one another; and etching the masks to reduce the different given thicknesses of the mask portions to a reduced thickness wherein the reduced thickness portions of the mask are of a uniform thickness.

Inventors: Liu; Shih-Chang (Yuku Village, TW), Chu; Wen-Ting (Kaohsiung County, TW), Lo; Chi-Hsin (Zhubei, TW), Tsai; Chia-Shiung (Hsin-Chu, TW)

Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.

International Classification: H01L 21/8247 (20060101)

Expiration Date: 8/31/12018