Patent Number: 7,786,621

Title: Circuit arrangement and method for reducing electromagnetic interference

Abstract: Circuit arrangement and method for reducing electromagnetic interference. The circuit arrangement includes a supply potential connection, a reference-ground potential connection, a controllable impedance element, a signal generator, and a circuit unit. The controllable impedance element is connected between the supply potential connection and the reference-ground potential connection, and has a control connection for receiving a control signal for controlling the impedance of the impedance element. The signal generator is coupled to the control connection of the impedance element. The circuit unit is connected between the supply potential connection and the reference-ground potential connection, and originates the electromagnetic interference during operation. The signal generator is designed to produce the control signal, which varies over time, in such a manner that the electromagnetic interference which originates from the circuit unit during operation is changed.

Inventors: Joodaki; Mojtaba (Dresden, DE)

Assignee: Qimonda AG

International Classification: H04B 3/30 (20060101)

Expiration Date: 8/31/12018