Patent Number: 7,786,743

Title: Probe tile for probing semiconductor wafer

Abstract: A tile used to hold one or more probes for testing a semiconductor wafer is disclosed. The tile has one or more sites for inserting one or more probes to test the semiconductor wafer. Each site has one or more holes. Each hole is coupled with a slot forming an angle. A probe is inserted into the tile from a top of the tile through the hole and seated on the slot. The probe has a probe tip. The probe top is in contact with the semiconductor wafer at one end of the slot at a bottom of the tile. The probe tip is aligned with an X and Y coordinate of a bond pad on the semiconductor wafer.

Inventors: Root; Bryan J. (Apple Valley, MN)

Assignee: Celadon Systems, Inc.

International Classification: G01R 31/02 (20060101)

Expiration Date: 8/31/12018