Patent Number: 7,786,770

Title: Reducing power consumption by disabling power-on reset circuits after power up

Abstract: Circuits and methods for reducing power consumption in an Integrated Circuit (IC) are provided. In one embodiment, a circuit includes a POR system control circuit, a POR latch and a control block circuit. The POR system control circuit generates a pulse during power up which is sent to the POR latch to set the state of the POR latch to a first logic state. The state of the POR latch is used to enable POR circuits during power up. The control block generates an output to disable POR circuits in the IC based on the state of the POR latch. After power-up, the state of the POR latch is set to a second logic state in order to disable the POR circuits resulting in power savings in the IC by eliminating static POR circuit current.

Inventors: Liang; Gwen G. (Palo Alto, CA), Vest; William Bradley (San Jose, CA)

Assignee: Altera Corporation

International Classification: H03K 17/22 (20060101)

Expiration Date: 8/31/12018