Patent Number: 7,786,771

Title: Phase lock loop (PLL) with gain control

Abstract: A Phase Lock Loop (PLL) with gain control is provided. The PLL has a dual-path configuration, where a first and a second VCO control voltage are generated in response to a phase or frequency difference between a PLL input signal and an output signal. The PLL comprises a dynamic voltage gain control (DVGC) unit and a voltage-to-current (V2I) unit, where the DVGC creates a baseline reference current in response to the first VCO control voltage and the V2I provides a substantially linear current in response to the second VCO control voltage. The currents from the DVGC and V2I are combined and fed into a current-controlled oscillator, which generates a PLL output frequency signal. Frequency gain of the VCO is substantially reduced, thus providing a PLL with improved tuning precision.

Inventors: Tsai; Tsung-Hsien (Hsin-Chu, TW), Hung; Tsung-Yang (Jhubei, TW), Chen; Chien-Hung (Taipei, TW), Yuan; Min-Shueh (Taipei, TW)

Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.

International Classification: H03L 7/06 (20060101)

Expiration Date: 8/31/12018