Patent Number: 7,786,786

Title: Multiphase clock for superconducting electronics

Abstract: A multiphase clock circuit in which bit errors are propagated only for the duration of the clock cycle in which a bit error occurs. The circuit recovers automatically from bit errors and is capable of operating at high frequency with high clock precision. The multiphase clock circuit can generate a plurality of clock pulse streams, each pulse stream at the same clock frequency, with fixed phase relationships among the streams. The multiphase clock circuit includes a master clock signal of frequency fc which is applied to a divide by N frequency divider circuit for producing a base clock signal of fc/N. The base clock signal is sequentially applied to the data input of a series chain of N clocked data flip-flops (DFFs) each of which is simultaneously clocked by a clock signal of frequency fc to produce N clock signals of base frequency fc/N separated from each other by a constant time delay T=1/fc.

Inventors: Kirichenko; Dmitri (Yorktown Heights, NY)

Assignee: Hypres, Inc.

International Classification: G06F 1/04 (20060101)

Expiration Date: 8/31/12018