Patent Number: 7,786,799

Title: Trimming technique for high voltage amplifiers using floating low voltage structures

Abstract: The system contains a first MOS transistor having a first source element, a first drain element, and a first gate element. A first low voltage current source has two ends. The ends of the low voltage current source are connected to at least two of the first MOS transistor elements. At least one first Zener clamp is in parallel with the low voltage current source.

Inventors: Bhattacharya; Anindya (Tucson, AZ), Cox; David F. (Tucson, AZ)

Assignee: Cirrus Logic, Inc.

International Classification: H03F 3/45 (20060101)

Expiration Date: 8/31/12018