Patent Number: 7,786,921

Title: Data processing method, data processing apparatus, semiconductor device, and electronic apparatus

Abstract: In a solid-state imaging device with an AD converter mounted on the same chip, to enable an efficient product-sum operation while reducing the size of the circuit scale and the number of transmission signal lines. A pixel signal during an n-row readout period is compared with a reference signal for digitizing this pixel signal, and a counting operation is performed in one of a down-counting mode and an up-counting mode while the comparison processing is being performed, and then, the count value when the comparison processing is finished is stored. Subsequently, by using the n-row counting result as the initial value, a pixel signal during an (n+1)-row readout period is compared with the reference signal for digitizing this pixel signal, and also, the counting operation is performed in one of the down-counting mode and the up-counting mode, and then, the count value when the comparison processing is finished is stored. If the count mode for the n+1 row is set to be opposite to the count mode for the n row, the count value obtained by the counting operation for the n+1 row is a subtraction result. If the count modes for the n+1 row and the n row are set to be the same, the count value obtained by the counting operation for the n+1 row is an addition result.

Inventors: Nitta; Yoshikazu (Tokyo, JP), Fukushima; Noriyuki (Kanagawa, JP), Muramatsu; Yoshinori (Kanagawa, JP), Yasui; Yukihiro (Kanagawa, JP)

Assignee: Sony Corporation

International Classification: H03M 1/34 (20060101)

Expiration Date: 8/31/12018