Patent Number: 7,787,148

Title: Dual printhead controller architecture having hidden slave

Abstract: Dual printhead controller architecture includes a master central processor capable of being interfaced with a first printhead. A slave central processor is capable of being interfaced with a second printhead. Data transfer means is operatively connected between the master central processor and the slave central processor to permit communication between the master and slave central processors. A host link is operatively connected to the master central processor to permit the master central processor to receive page data from a host processor. The master central processor is configured so that the slave central processor is hidden from the host processor.

Inventors: Lapstun; Paul (Balmain, AU), Silverbrook; Kia (Balmain, AU)

Assignee: Silverbrook Research Pty Ltd

International Classification: G06F 15/00 (20060101); G06K 1/00 (20060101); G06K 15/10 (20060101); G06F 3/12 (20060101)

Expiration Date: 8/31/12018