Patent Number: 7,787,286

Title: SRAM memory with reference bias cell

Abstract: A random access memory microelectronic device, comprising a plurality of cells comprising respectively: a plurality of transistors forming a bistable, a first storage node and a second storage node, a first double gate access transistor to the first storage node and a second double gate access transistor to the second storage node, a first gate of the first access transistor and a first gate of the second access transistor being linked to a first word line, a second gate of the first access transistor and a second gate of the second access transistor being linked to a second word line, the device being moreover equipped: with a reference memory cell provided to deliver a bias potential intended to be applied to one of the respective word lines of one or several given cells of said plurality of cells during reading access of said given cells.

Inventors: Thomas; Olivier (Revel, FR)

Assignee: Commissariat a l'Energie Atomique

International Classification: G11C 11/00 (20060101)

Expiration Date: 8/31/12018