Patent Number: 7,787,290

Title: Semiconductor device

Abstract: In MRAM using a spin-transfer torque switching, a sufficient writing operation with a small memory cell is realized, and a reading current is enlarged while a reading disturbance is suppressed. In the case where the free layer of the tunnel magneto-resistance element is located on the side of the bit line, using a PMOS transistor, and in the case where the fixed layer of the tunnel magneto-resistance element is located on the side of the bit line, using an NMOS transistor, an anti-parallel writing in a source grounding operation is performed. The reading and writing operation margin is improved by performing a reading operation in an anti-parallel writing direction.

Inventors: Takemura; Riichiro (Tokyo, JP), Kawahara; Takayuki (Higashiyamato, JP), Ito; Kenchi (Kunitachi, JP), Takahashi; Hiromasa (Hachioji, JP)

Assignee: Hitachi, Ltd.

International Classification: G11C 11/00 (20060101)

Expiration Date: 8/31/12018