Patent Number: 7,787,314

Title: Dynamic real-time delay characterization and configuration

Abstract: In mask programmable integrated circuit, such as a structured ASIC, a delay chain provides a delay that is set by a mask programmable switch. The delay chain receives an input to allow the delay mask programmed delay to be overridden using a JTAG controller. This allows testing of different delays. The input may also be provided by a fuse block, so that the fuse block can override the mask programmable switch, thus allowing a delay to be changes after mask programming.

Inventors: Tan; Jun Pin (Kuala Lumpur, MY), Koay; Wei Yee (Penang, MY), Ang; Boon Jin (Penang, MY), Wong; Choong Kit (Penang, MY), Soh; Guang Sheng (Gemas, MY)

Assignee: Altera Corporation

International Classification: G11C 7/10 (20060101)

Expiration Date: 8/31/12018