Patent Number: 7,787,318

Title: Semiconductor memory device having read operation testing function

Abstract: A semiconductor memory device is provided which can reliably detect a memory cell which has an unstable operation due to a small memory cell current. A bit line drive circuit is provided with respect to each pair of first and second bit lines, and has a configuration which can decrease a potential of a selected one of the pair of first and second bit lines. During a test operation, the first bit line in conduction with an H-side memory holding node of a memory cell is grounded for a predetermined time, thereby reducing a potential difference between the pair of first and second bit lines.

Inventors: Satomi; Katsuji (Osaka, JP)

Assignee: Panasonic Corporation

International Classification: G11C 29/00 (20060101); G11C 7/00 (20060101)

Expiration Date: 8/31/12018