Patent Number: 7,787,325

Title: Row decode driver gradient design in a memory device

Abstract: A memory device using a plurality of enhanced row decode drivers for activating wordlines in a memory array is disclosed. Circuit design attributes of the enhanced row decode drivers are varied as a function of proximity to a source of a row address signal applied to each decode driver. The circuit variations are operable to reduce the leakage power of the driver by degrading performance thereof while maintaining required worst case timing. The worst case timing being defined by the timing and performance requirements for the most distant of the row decode driver circuits relative to the source of the applied row address signals.

Inventors: Brown; Jeffrey S. (Fort Collins, CO), Byrn; Jonathan W. (Fort Collins, CO), Turner; Mark F. (Longmont, CO)

Assignee: LSI Corporation

International Classification: G11C 8/00 (20060101)

Expiration Date: 8/31/12018