Patent Number: 7,788,312

Title: Apparatus and method for reducing errors in analog circuits while processing signals

Abstract: A method and apparatus processes signals in a set of analog circuit components of an analog circuit white enforcing a set of explicit constraints corresponding to a set of implicit constraints to reduce errors in output signals.

Inventors: Vigoda; Benjamin Butterfly William (Somerville, MA)

Assignee: Mitsubishi Electric Research Laboratories, Inc.

International Classification: G06G 7/00 (20060101)

Expiration Date: 8/31/12018