Patent Number: 7,788,443

Title: Transparent multi-hit correction in associative memories

Abstract: A mechanism is provided for transparent multi-hit correction in associative memories. A content associative memory (CAM) device is provided that transparently and independently executes a precise corrective action in the case of a multiple hit being detected. The wordlines of a CAM array are modified to include a valid bit storage circuit element that indicates whether or not the corresponding wordline is valid or not. In operation, if multiple hits are detected, the multiple hit is signaled to the host system and the particular entries in the CAM array corresponding to the multiple hits are invalidated by setting their associated valid bit storage circuit elements to an invalid value or clearing the value in the associated valid bit storage circuit element. Any data returned to the host system as a result of the multiple hits is invalidated in the host system in response to the signaling of the multiple hits.

Inventors: Lee; Michael J. (Austin, TX), Ramadurai; Vinod (South Burlington, VT), Truong; Bao G. (Austin, TX)

Assignee: International Business Machines Corporation

International Classification: G06F 13/00 (20060101); G06F 11/00 (20060101); G11C 15/00 (20060101); G06F 13/28 (20060101)

Expiration Date: 8/31/12018