Patent Number: 7,788,448

Title: Sequencer cache and method for operating the same

Abstract: A cache system includes a cache memory dedicated to service a number of sequencers with sequencer code. A number of cache managers are defined to direct placement of sequencer code portions into the cache memory. Also, each of the number of cache managers is defined to provide sequencer code from the cache memory to a respectively assigned sequencer. An external memory is defined to store a complete version of the sequencer code. A direct memory access (DMA) engine is defined to write sequencer code portions from the external memory to the cache memory, in accordance with direction from the number of cache managers.

Inventors: Spitzer; Marc (San Jose, CA)

Assignee: PMC-Sierra US, Inc.

International Classification: G06F 12/00 (20060101)

Expiration Date: 8/31/12018