Patent Number: 7,788,452

Title: Method and apparatus for tracking cached addresses for maintaining cache coherency in a computer system having multiple caches

Abstract: A computer system includes multiple caches and a cache line state directory structure, having at least a portion dedicated to a particular device cache within a particular device, and contains a fixed number of entries having a one-to-one correspondence to the cache lines of the cache to which it corresponds. The cache line state directory is used to determine whether it is necessary to send an invalidation message to the device cache. In the preferred embodiment, a dedicated portion of the cache line state directory structure corresponds to an I/O bridge device cache. Preferably, the cache line state directory also maintains state for one or more processor caches in a different format. The computer system preferably uses a NUMA architecture, the directories being maintained by node servers in each node.

Inventors: Averill; Duane Arlyn (Rochester, MN), Hoover; Russell Dean (Rochester, MN), Shedivy; David Alan (Rochester, MN), Voytovich; Martha Ellen (Rochester, MN)

Assignee: International Business Machines Corporation

International Classification: G06F 13/00 (20060101); G06F 15/76 (20060101)

Expiration Date: 8/31/12018