Patent Number: 7,788,563

Title: Generation of test sequences during memory built-in self testing of multiple memories

Abstract: The present invention concerns an apparatus including a modular memory and an address locator circuit. The modular memory may be configured to generate a current address signal, a first data output signal and a second data output signal in response to a first port address signal, a second port address signal, an initial state parameter, a target state parameter, a first port enable signal, a second port enable signal, a write enable signal, a data input signal, a first location signal and a second location signal. The address locator circuit may be configured to generate the first location signal and the second location signal in response to the first port address signal, the second port address signal and the current address signal.

Inventors: Andreev; Alexandre E. (San Jose, CA), Bolotov; Anatoli A. (Cupertino, CA), Scepanovic; Ranko (Saratoga, CA)

Assignee: LSI Corporation

International Classification: G01R 31/28 (20060101)

Expiration Date: 8/31/12018