Patent Number: 7,788,573

Title: Fault detection method, test circuit and semiconductor device

Abstract: A fault detection method for detects, within a semiconductor device, a fault in a delay chain that is provided within the semiconductor device and is made up of delay parts that are each formed by delay cells. The method judges if a fault exists in a first specific delay cell within a first delay part when testing the first specific delay cell, by detecting a first relative delay time between input and output signals of the first specific delay cell, and processing the first relative delay time at a timing based on an output of a delay cell within a second delay part that is provided at a stage preceding or subsequent to the first delay part. The method judges if a fault exists in a second specific delay cell within the second delay part exists when testing the second specific delay cell, by detecting a second relative delay time between input and output signals of the second specific delay cell, and processing the second relative delay time at a timing based on an output of a delay cell within the first delay part.

Inventors: Yamanaka; Hiroaki (Kawasaki, JP)

Assignee: Fujitsu Semiconductor Limited

International Classification: G06F 11/00 (20060101); G01R 31/28 (20060101)

Expiration Date: 8/31/12018