Patent Number: 7,788,614

Title: Method and apparatus for performing analytic placement techniques on logic devices with restrictive areas

Abstract: A method for designing a system on a target device having restricted areas includes determining locations on the target device for all cells in the system by solving one or more equations. The one or more equations are modified, or supplemented by adding one or more additional equations, by applying spreading forces to the cells that take into consideration classification types of the cells and restricted areas on the target device that do not support the classification types. Revised locations on the target device are determined for the cells by solving the modified one or more equations.

Inventors: Galloway; David (Toronto, CA), Fung; Ryan (Mississauga, CA)

Assignee: Altera Corporation

International Classification: G06F 17/50 (20060101)

Expiration Date: 8/31/12018