Patent Number: 7,820,459

Title: Methods relating to the reconstruction of semiconductor wafers for wafer level processing including forming of alignment protrusion and removal of alignment material

Abstract: Methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in a similar pattern protruding from a substrate to position the dice through surface tension interaction. The alignment droplets are then solidified to maintain the positioning and an underfill is disposed between the dice and the fixture to strengthen and maintain the reconstructed wafer. A fixture plate may be used in combination with the underfill to add additional strength and simplify handling. The reconstructed wafer may be subjected to wafer-level processing, wafer-level testing and burn-in being particularly facilitated using the reconstructed wafer. Alignment droplets composed of sacrificial material may be removed from the reconstructed wafer and the resulting void filled to form interconnects or contacts on the resulting dice.

Inventors: Tan; Yong Kian (Singapore, SG), Tay; Wuu Yean (Singapore, SG)

Assignee: Micron Technology, Inc.

International Classification: H01L 21/66 (20060101); H01L 21/46 (20060101); H01L 21/48 (20060101); H01L 21/44 (20060101); H01L 21/50 (20060101)

Expiration Date: 2018-10-26 0:00:00