Patent Number: 7,820,538

Title: Method of fabricating a MOS device with non-SiO.sub.2 gate dielectric

Abstract: A polycrystalline silicon layer is deposited on a gate dielectric and then a portion thereof is re-oxidized so as to form a thin layer of oxide between the poly-Si layer and the underlying gate dielectric. Subsequently, the poly-Si layer is converted to a fully-silicided form so as to produce a FUSI gate. The gate dielectric can be a high-k material, for example a Hf-containing material, or SION, or another non-SiO.sub.2 dielectric. The barrier oxide layer is preferably less than 1 nm thick.

Inventors: Kaushik; Vidya (Hoeilaart, BE)

Assignee: Freescale Semiconductor, Inc.

International Classification: H01L 21/3205 (20060101)

Expiration Date: 2018-10-26 0:00:00