Patent Number: 7,821,050

Title: CRAM transistors with high immunity to soft error

Abstract: A transistor fabricated on a semiconductor substrate includes a source and a drain in the substrate; a gate on the substrate, the gate being insulated from the substrate by gate dielectric; barrier layers covering two sides of the gate and the gate dielectric; spacers of high-k material covering the barrier layers; and nitride spacers covering the spacers of high-k material. The spacers of high-k material significantly increase the node capacitance of the transistor and therefore reduce the transistor's soft error rate.

Inventors: Liu; Yowjuang (Bill) (San Jose, CA), Huang; Cheng-Hsiung (Cupertino, CA), Shih; Chih-Ching (Pleasanton, CA)

Assignee: Altera Corporation

International Classification: H01L 27/108 (20060101); H01L 29/94 (20060101)

Expiration Date: 2018-10-26 0:00:00