Patent Number: 7,821,276

Title: Method and article of manufacture to generate IC test vector for synchronized physical probing

Abstract: Systems, methods, and computer readable media storing instructions for such methods relate to generating test vectors that can be used for exercising a particular area of interest in an integrated circuit. The test vectors generally include a non-overlapping repeating and/or predictable sequence of care bits (a care bit pattern) that can be used by a tester to cause the exercise of the area and collect emissions caused by exercising the area. Such emissions can be used for analysis and debugging of the circuit and/or a portion of it. Aspects can include providing a synchronization signal that can be used by a tester to allow sensor activation at appropriate times.

Inventors: Swenton; Joseph (Owego, NY), Bartenstein; Thomas (Owego, NY), Schoonover; Richard (Binghamton, NY), Sliwinski; David (Vestal, NY)

Assignee: Cadence Design Systems, Inc.

International Classification: G01R 31/302 (20060101)

Expiration Date: 2018-10-26 0:00:00