Patent Number: 7,821,292

Title: Impedance calibration period setting circuit and semiconductor integrated circuit

Abstract: An impedance calibration period setting circuit includes a command decoder and an impedance calibration activation signal generator. The command decoder combines external signals to generate a refresh signal. The impedance calibration activation signal generator is configured to generate an impedance calibration activation signal in response to the refresh signal and an address signal. The impedance calibration period setting circuit prevents abnormal changes in an impedance calibration code and reduces current consumption.

Inventors: Yang; Ji Yeon (Gyeonggi-go, KR), Lee; Dong Uk (Gyeonggi-do, KR)

Assignee: Hynix Semiconductor Inc.

International Classification: H03K 17/16 (20060101); H03K 19/003 (20060101)

Expiration Date: 2018-10-26 0:00:00