Patent Number: 7,821,436

Title: System and method for reducing power dissipation in an analog to digital converter

Abstract: A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and-hold phase and an amplifying phase for sampling and amplifying an analog input signal respectively, eliminating an effect of load on a residue amplifier when amplifying the residue output to generate an amplified residue output in the amplifying phase, and eliminating an effect of small feedback factor when sampling the amplified residue output in the sample-and-hold phase. Power advantage is achieved by sharing the load on the residue amplifier across the sample-and-hold phase and the amplifying phase rather than being fully present in any one of the clock phases. The present invention also provides a method for reducing the number of comparators used in ADCs.

Inventors: Teeka Srinvasa Setty; Venkatesh (Bangalore, IN), Lakshminarayanan; Chandrashekar (Thanjavur, IN), Kali Bhattacharya; Prasun (Burdwan, IN), Bhowmik; Prasenjit (Agartala, IN), Srinivasan; Chakravarthy (Bangalore, IN), Khatri; Mukesh (Indore, IN), Kumar Ghosh; Sanjeeb (Chandan-Pukur, IN), Chakkirala; Sumanth (Vasco-da-gama, IN), Krishnan; Sundararajan (Bangalore, IN), Easwaran; Prakash (Bangalore, IN)

Assignee: Cosmic Circuits Private Limited

International Classification: H03M 3/00 (20060101)

Expiration Date: 2018-10-26 0:00:00